Scan chains are commonly designed into semiconductor integrated circuits (or “devices”) for testing and analyzing performance of the circuits. Typically, scan chain comprises a series of flip-flop circuits arranged much like a shift register. A single input pin can be used to clock data into the scan chain and, conversely, a single output pin on the device can be used to clock data out of the scan chain.
In a typical circuit, there may be hundreds or even thousands of scan chains. The scan chains may be multiplexed to utilize a limited number of I/O pins. Further, each scan chain may comprise hundreds or even thousands of flip-flop circuits. Accordingly, detecting, identifying and physically locating a failure in a scan chain can be particularly challenging.